SONIC will achieve its mission by structuring its research agenda to employ three top-down systems-driven themes complemented by an experimental bottom-up hybrid devices and circuits theme. SONIC will harness innovations in systems in order to achieve the goal of enabling equivalent scaling in beyond-CMOS fabrics.

SONIC was established in January 2013 with three top-down system-driven themes (Themes 1, 2, and 3) which employ Shannon and brain-inspired approaches for information processing on extremely scaled nanofabrics. Our approach is referred to as statistical information processing. The system-driven themes develop design principles, statistical information processing architectures, and create experimental prototypes in collaboration with Theme 4.

2013 through mid 2015

a graphical representation of the organization of the SONIC center from 2013 to mid 2015
(click image to enlarge)

Mid 2015 through 2017

a graphical representation of the SONIC center from mid 2015 through 2017
(click image to enlarge)

Since mid-Year 3 (April 2015), SONIC has gone through a mid-program re-alignment based on lessons learned from the first 2.5 years of operation. A key lesson – the journey from system theory through architecture to CMOS, beyond CMOS, and FPGA prototypes can be demonstrated for specific algorithms and applications, resulting in statistical information processing system designs that exhibit unprecedented gains in energy efficiency and throughput over conventional methods.

Moving forward, while Themes 1, 2, and 3 continue to be systems-driven, these themes, particularly Theme 1, has an increased emphasis on developing generalized design principles, and obtaining fundamental limits on information processing capacity, energy efficiency and throughput. In-sensor and in-memory computing emerged as two promising platforms that can effectively showcase SONIC's Shannon and brain-inspired approach to information processing on deeply scaled process technologies. These are being explored extensively.

Theme 4 has transitioned out device characterization and is emphasizing the design and fabrication of nanofunctions commonly employed in inference applications, and providing models of these to SONIC's system themes. Prototyping of promising designs in CMOS and beyond will be a priority as before. SONIC's unified design and materials-devices-driven research agenda will provide the radical transformation necessary to enable continued scaling in the beyond-CMOS era. It will be dramatically different from the previous, historically bottom-up materials-devices-driven approach to scaling and Moore's law.